1. Field of the Invention
The present invention relates to a spread spectrum clock generation circuit which generates clock signals having a minutely varying cycle to reduce electromagnetic interference emission and a method of controlling the spread spectrum clock generation circuit.
2. Description of Related Art
FIG. 9 shows the configuration of the spread spectrum clock generation circuit (hereinafter referred to as “SSCG circuit”) 200 disclosed in Japanese Unexamined Patent Publication No. 2004-207846. An analog modulator 119 generates a modulation signal VF according to control performed by a switching control circuit 120. The modulation signal VF is added to a control signal VLF in a voltage adder circuit 116. Then, the voltage adder circuit 116 outputs a control signal VIN.
FIG. 10 illustrates the circuit configuration of the switching control circuit 120 and the analog modulator 119 which are shown in FIG. 9. As shown in FIG. 10, the analog modulator 119 includes three capacitor elements C101 to C103 having different capacitance values. Herein, the capacitance values of these capacitor elements are set so as to satisfy C101<C102<C103. The capacitor elements are grounded at one end and connected, at the other end, to selector switches SW101 to SW103 respectively so that they are connected to one another through the switches. Switching of each switch between conductive/non-conductive states is controlled by the switching control circuit 120. A charger/discharger unit 104 is a current source circuit in which a current mirror circuit charges or discharges a common terminal connected to the switches SW101 to SW103, by supplying or getting rid of a current equal to a current i flowing in a constant current circuit. The common terminal to which the switches SW101 to SW103 are connected is an output terminal for an analog modulator. This terminal is connected to a hysteresis comparator 134 provided for a voltage fluctuation range detector 105. The hysteresis comparator 134 compares an input voltage of the common terminal for the switches SW101 to SW103 with first and second reference values; controls transistors Tr101 and Tr102 of the current source circuit according to the result of the comparison; and switches the current source circuit from its conductive state to its non-conductive state or vice versa.
Herein, the voltage of the control signal VIN is allowed to minutely fluctuate up and down thereby causing slight variations in the frequency of an output signal CK. The analog modulator 119 shown in FIG. 10 makes the voltage of the modulation signal VF vary minutely, thereby causing the control signal VIN to vary minutely through the voltage adder circuit 116.
Expediently, the state where PLL is locked is herein called “the initial state”. In this state, the output signal CK has a frequency that is obtained by multiplying the frequency of a basic clock signal CLK by M/N. If a current is supplied to VF from the charger/discharger unit in this condition, the voltage of the modulation signal VF rises and the voltage of the control signal VIN rises through the voltage adder circuit 116 so that the frequency of the output signal CK slightly increases. When the voltage of the modulation signal VF reaches a certain value, a detection signal DS output from the voltage fluctuation range detector 105 becomes “H (high level)” so that the transistor Tr102 becomes electrically conductive and therefore the charge/discharge unit 104 starts discharging. Thereby, the voltage of the modulation signal VF starts to drop with a gradual decrease in the frequency of the output signal CK. At the time when the voltage of the modulation signal VF reaches a certain value after further decreasing, the detection signal DS becomes “L (low level)” and the transistor Tr101 becomes conductive, so that the charger/discharger unit 104 starts charging. This operation is repeated whereby the frequency of the output signal CK minutely varies. The capacitor elements C101 to C103 are switched by the switching control circuit 120 to change capacitance, so that combined modulation can be carried out to vary the minutely varying cycle (i.e., modulation cycle) of the frequency, which enables a reduction in electromagnetic interference emission.
FIG. 11 shows an SSCG circuit 200a according to the second configuration example of Japanese Unexamined Patent Publication No. 2004-207846. The SSCG circuit 200a shown in FIG. 11 differs from the first SSCG circuit 200 in that the former includes a voltage-current conversion (V-I conversion) circuit 242, a current digital-analog converter (IDAC) 243, a current control oscillator (ICO) 244 and a control circuit 241. The voltage-current conversion circuit 242 converts the terminal voltage (differential voltage) of a loop filter 214 into a differential current signal Iref. The current digital-analog converter 243, which is equivalent to a variable current circuit, performs spread spectrum modulation of the differential current signal Iref according to an output code from the control circuit 241 and releases a modulated spread spectrum modulation current signal IO to the current control oscillator (ICO) 244.
FIG. 12 shows a configuration of the control circuit 241. The control circuit 241 includes (i) three dividers 251 to 253 for dividing a control clock at different dividing ratios (herein, 1/9, 1/10 and 1/11 are employed); (ii) switches 255 to 257 for selecting an output of any of the dividers; (iii) a switching control unit 254 for selecting any of the switches; (iv) an up-down counter 258 for counting selected divided clocks; and (v) a divider counter for controlling the up-down counter 258. The up-down counter 258 outputs a binary-coded counter value having n bits.
FIG. 13 shows the operations of the up-down counter 258 and the divider counter 259. The up-down counter 258 counts selected divided clocks and outputs a count value in n-bit, binary-coded form. The code output from the up-down counter 258 is applied to the digital-analog converter 243.
As shown in FIG. 14, the digital-analog converter 243 has a current mirror circuit comprised of transistors Tr211 to Tr215, Tr220, Tr230 to Tr23n, and the sizes of the transistors are appropriately set as shown in the figure. Accordingly, a proper amount of current ranging from 90% to about 110% of the differential current signal Iref is output as the spread spectrum modulation current signal IO, by setting the bit data /DO to /Dn of the output code to proper values.
Techniques related to the above-described method are disclosed in Japanese Unexamined Patent Publication Nos. 2000-101424 and 2000-36741.